library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--entity test1 is port(
--	a,b,c,d: in std_logic;
--	e: out std_logic
--);
--end entity test1;

--architecture bhv of test1 is
--	signal x,y: std_logic;
--begin
--p1:process(a,b,c,d)
--	begin
--	x <= a and b;
--	y <= c and d;
--	e <= x or y;
--	end process p1;
--end architecture bhv;
entity test1 is port(
	r,s: in STD_logic;
	q,qb: inout STD_logic
);
end entity test1;
architecture bhv of test1 is
begin 
	q <= s nand qb;
	qb <= r nand q;
end architecture bhv;
	